Generally, clock signals are used as a reference for setting the operation timing in a system or a circuit, or they are used to secure fast operation without error. When a clock signal from an external clock source is used inside a circuit, a clock skew occurs in the circuit. Thus, a delay locked loop (DLL) is used to get the internal clock signal to have the same phase as the external clock.
Significant elements required for a DLL are small area, little jitter and fast locking time. These characteristics may still be required for next-generation semiconductor devices that consumes low electric power and operates fast. However, conventional technologies have fulfilled only a few parts of these requirements, and thus have showed limitations on the low-power and fast operation.
Compared with a phase locked loop (PLL), a DLL has an advantage that it is less affected by noise so it is used widely for synchronous semiconductor memories including a double data rate synchronous dynamic RAM (DDR SDRAM). Among DLLs, most frequently used is a register controlled DLL, which will be described in detail along with the disadvantages of related conventional technologies, hereinafter.
FIG. 1 is a block diagram illustrating a register controlled delay locked loop (DLL) of a conventional double data rate (DDR) synchronous dynamic RAM (SDRAM).
A register controlled DLL of a conventional DDR SDRAM comprises a delay block 10, a first clock buffer 11 to receive an external clock inverse-signal /clk for generating an internal clock signal fall_clk in synchronization with a falling edge of an external clock signal clk, a second clock buffer 12 to receive an external clock signal clk for generating an internal clock signal rise_clk in synchronization with a rising edge of an external clock signal clk, and a clock divider 13 to divide the internal clock signal rise_clk by 1/n (n being a positive integer, commonly n=8) and to output a delay monitoring clock signal dly_in and a reference clock signal ref. The delay block 10 includes a first delay line 14 to delay the internal clock signal fall_clk, a second delay line 15 to delay the internal clock signal rise_clk, and a third delay line 16 to delay the delay monitoring clock signal dly_in. The register controlled DLL also includes a first DLL driver 20 to drive a DLL clock signal fclk_dll in response to an output ifclk of the first delay line 14, a second DLL driver 21 to drive a DLL clock rclk_dll in response to an output signal irclk of the second delay line 15, a delay model 22 to receive an output feedback_dly of the third delay line 16 and has the clock signal feedback_dly go through the same delaying condition as the actual clock path, a phase comparator 19 to compare an output signal feedback of the delay model 22 with the reference clock signal ref in their phase, and a delay control signal generation block 23.
Here, the delay model 22 (also called a replica circuit) includes a dummy clock buffer, a dummy output buffer and a dummy load. The control signal generation block 23 includes a shift register 17 and a shift controller 18 to control the first to third delay lines 14, 15, 16 in the delay block 10. The shift register 17 determines an amount of delay time in the first to third delay lines 14, 15, 16. The shift controller 18 outputs a delay locking signal dll_lockb, that indicates the completion of a locking and shift control signals SR and SL for controlling the delay time of the first to third delay lines 14, 15, 16 based on the value stored in the shift register 17 in response to a phase comparison signals PC<0:4> outputted from the phase comparator 19.
The operation of a conventional register controlled DLL constructed as above will be described hereinafter. First, the first clock buffer 11 generates the internal clock signal fall_clk in response to the falling edge of an external clock signal clk. The second clock buffer 12 also generates the internal clock signal rise_clk in response to the rising edge of an external clock signal clk. The clock divider 13 divides the internal clock signal rise_clk into the two signals, i.e., the reference clock signal ref and the delay monitoring clock signal dly_in whenever the nth external clock signal is inputted into the DLL where “n” is a function of the clock divider 13.
In the initial operation, the divided clock signal dly_in passes through only one unit delay element in the third delay unit 16 of the delaying block 10. The third delay unit 16 outputs the clock signal feedback_dly, which goes through the delay model 22 again. The clock signal feedback_dly is delayed and outputted as the output signal feedback by the delay model 22.
The phase comparator 19 compares a rising edge of the reference clock signal ref with a rising edge of the feedback clock signal feedback and generates phase comparison signals PC<0:4>. The shift controller 18 outputs shift right and left signals SR and SL for controlling the shift direction of the shift register 17 in response to the phase comparison signals PC<0:4>. The shift register 17 determines the amount of delay time the first to third delay lines 14, 15, 16 in response to the shift right or left signal SR or SL. When a shift right signal SR is issued, the register 17 makes the first to third delay units 14, 15, 16 shift in a right direction whereas a shift left signal SL is issued, the register makes the first to third delay units 14, 15, 16 shift in a left direction.
A locking is achieved in a moment when the two clock signals have a minimum jitter between the feedback clock signal of controlled delay amount with the reference clock signal ref. As a delay locking signal dll_lockb is outputted from the shift controller 18, the first and second DLL drivers 20 and 21 are activated, and the DLL clock signals fclk_dll and rclk_dll operate with the same phase as the external clock signal clk.
In general, the DLL operates as described above and a circuit operates by using an internal clock signal determined thereby. Because data are not transmitted outside during a self-refresh operation, the internal clock signals by the operation of the DLL are not needed. As a result, the shift register 17 is reset and all DLL internal operations are reduced as much as possible. The self-refresh operation of the DLL will be described more in detail, hereinafter.
Because the first and second clock buffers 11 and 12 do not receive any external clock signals clk and /clk, the internal clock signals fall_clk and rise_clk are in a low state ‘L’. As the clock divider 13 is operated by receiving the internal clock signals fall_clk and rise_clk outputted from the first and second clock buffers 11, 12, the delay monitoring clock signal dly_in is kept in a low state ‘L’ and the reference clock, in a high state ‘H’.
FIG. 2 is a circuit diagram depicting a phase comparator 19 in the conventional register controlled DLL, and FIG. 3 is a timing diagram of the phase comparator 19 in the conventional register controlled DLL. The phase comparator 19 receives reference clock signal ref in a high state ‘H’ from the clock divider 13 and feedback clock signal feedback in a low state ‘L’ from the delay lines and the delay model, and the phase comparison signal PCO stays in the low state ‘L’. As the phase comparison signal PCO is in a low state ‘L’, nodes A-5, A-6, B-5 and B-6 are maintained at a high state ‘H’, and the NAND latch circuit coming thereafter continues to latch the values it has kept. If the phase comparison signals PC1 and PC3 are in a high state ‘H’, the two signals are maintained in the high state ‘H’ continuously during the self-refresh operation and the phase comparison signals PC2 and PC4 latches a low state ‘L’.
FIG. 4A is a circuit diagram of a shift controller 18 in a conventional register controlled DLL, and FIG. 4B is a timing diagram of a shift controller 18 in a conventional register controlled DLL. The shift controller 18 receives phase comparison signals PC<0:4> generated in the phase comparator 19 and generates a signal controlling the shift register 17.
Because the phase comparison signal PC0 is in a low state ‘L’, an even pulse signal PE and an odd pulse signal PO outputted from a pulse generator 401 are maintained in the low state ‘L’ and the high state ‘H’, respectively. The pulse generator 401 receives the phase comparison signal PC0 and generates new pulse signals in accordance with the rising edge and falling edge. In case the phase comparison signals PC1 and PC3 are all in a high state ‘H’, a shift right control signal SCR is generated through a NAND gate 403 and an inverter 405. In case the phase comparison signals PC2 and PC4 are all in a high state ‘H’, a shift left control signal SCL is generated through a NAND gate 407 and an inverter 409.
Combinations of the even pulse signal PE, odd pulse signal PO, shift right control signal SCR, and shift left control signal SCL generate a shift right odd signal SRO, shift right even SRE, shift left odd SLO, and shift left even SLE. In particular, the phase comparison signals PC1 and PC3 are in a high state ‘H’ and the even pulse signal PE is in a high state ‘H’, the shift right even SRE is generated. If the phase comparison signals PC1 and PC3 are in a high state ‘H’ and the odd pulse signal PO is in a high state ‘H’, the shift right odd SRO is generated. If the phase comparison signals PC2 and PC4 are in a high state ‘H’ and the even pulse signal PE is in a high state ‘H’, the shift left even SLE is generated. If the phase comparison signals PC2 and PC4 are in a high state ‘H’ and the odd pulse signal PO is in a high state ‘H’, the shift left odd SLO is generated. In short, during the self-refresh operation, one of the shift right even SRE, shift right odd signal SRO, shift left even SLE and shift left odd SLO signals are maintained in the high state ‘H’ continuously by the value that had been kept before the self-refresh operation entry.
FIG. 5 is a circuit diagram of a shift register 17 in a conventional register controlled DLL. During the self-refresh operation, the shift register 17 receives a reset signal in a high state ‘H’ and resets all the values it has. That is, if the reset signal is in a high state ‘H’, it passes through the inverter 501 and is converted into a state where a reset bar signal is ‘L’.
To describe the operation of LATCH1, a NAND gate 503-1 receiving a reset bar signal converts the voltage level on node R-1 into a high state ‘H’, and the inverter 505-1 receiving the value on node R-1 converts the voltage level on node R-2 into a low state ‘L’. Likewise, in a LATCH2, a NAND gate 503-2 receiving the reset bar signal converts the voltage level on node R-3 into a high state ‘H’, and the inverter 505-2 receiving the value on node R-3 converts the voltage level on node R-4 into a low state ‘L’. Consequently, the NMOS transistor 511-2 receiving the value on node R-2 is turned off, while the NMOS transistor 513-1 receiving the value on node R-3 is turned on.
Here, the NMOS transistor 511-1 is turned on as an external power Vcc is connected to its gate. Therefore, when the SRO signal is in a high state ‘H’ during the period of self-refresh operation, the NMOS transistor 507-1 and the NMOS transistor 511-1 are all turned on, and because the NAND gate 503-1 receiving a reset bar signal continues to keep the voltage level on node R-1 in a high state ‘H’, an unnecessary electric current (marked with a thick line in FIG. 5) gets to run during the period of the self-refresh operation.